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93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.9
Write All (WRAL)
The DO pin indicates the Ready/ Busy status of the
The Write All ( WRAL ) instruction will write the entire
memory array with the data specified in the command.
device if CS is brought high after a minimum of 250 ns
low (T CSL ).
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command includes an automatic ERAL cycle for the
device, so the WRAL instruction does not require an
ERAL instruction. However, the chip must be in the
EWEN status.
Note:
Note:
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/ Busy status from DO.
V CC must be ? 4.5V for proper operation of WRAL.
FIGURE 2-7:
WRAL TIMING
T CSL
CS
CLK
DI
1
0
0
0
1
x
???
x
Dx
???
D0
T SV
T CZ
DO
High-Z
Busy
Ready
H IGH -Z
T WL
? 2003-2012 Microchip Technology Inc.
DS21796M-page 9
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